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Ordering number : ENN4212A
CMOS IC
LC86P6032
8-Bit Single Chip Microcontroller with One-Time PROM
Overview
The LC86P6032 microcontroller, a new addition to the LC866000 series, is a 8-bit single chip CMOS microcontroller with one-time PROM. This microcontroller has the same function and pin assignment as for the LC866000 series mask ROM version, and a 32K-byte PROM.
Features
(1) Option switching using PROM data The optional functions of the LC866000 series can be specified using PROM data. The functions of the trial products can be evaluated using a mass production board. (2) Internal one-time PROM capacity : 32768 bytes (3) Internal RAM capacity : 512 bytes
Mask ROM version LC866032 LC866028 LC866024 LC866020 LC866016 LC866012 LC866008 PROM capacity 32512 bytes 28672 bytes 24576 bytes 20480 bytes 16384 bytes 12288 bytes 8192 bytes RAM capacity 512 bytes 512 bytes 512 bytes 384 bytes 384 bytes 384 bytes 384 bytes
(4) Operating supply voltage : 4.5V to 6.0V (5) Instruction cycle time : 0.98s to 400s (6) Operating temperature range : -30C to +70C (7) Pin and package compatible with the mask ROM version (8) Applicable mask ROM version : LC866032/LC866028/LC866024/LC866020/LC866016/LC866012 /LC866008 (9) Factory shipment : DIP64S : QFP64E
Programming service
We offer various services at nominal charges. These include ROM writing, ROM reading, and package stamping and screening. Contact our local representatives for further information.
Ver.1.02G 31293
91400 RM (IM) TW No.4212-1/22
LC86P6032
Notice for use
When using, please take note of the following. (1) Differences between the LC86P6032 and the LC866000 series
Item Port status at reset Operation after releasing reset LC86P6032 LC866032/28/24/20/16/12/08 Please refer to "Port status at reset" on the next page. The option is specified by degrees within The program located at 00H is executed 3ms after applying a `H' level to the reset immediately after applying a `H' level to pin. the reset pin. The program located at 00H is executed. Pulldown resistor Pulldown resistor : Provided/Not provided Not provided Specified by the option Provided(fixed) Provided(fixed) Provided(fixed) Specified by the option Not provided Specified by the option 4.5V to 6.0V 2.5V to 6.0V Refer to "electrical characteristics" on the semiconductor news.
Output form of segment *S0/T0 to S6/T6 *S7/T7 to S15/T15 *S16 to S23 *S24 to S29 Operating supply voltage range (VDD) Power dissipation
LC86P6032 uses 256 bytes that is addressed on 7F00H to 7FFFH in the program memory as the option configuration data area. This option configuration cannot execute all options which LC866000 series have. Next tables show the options that correspond and not correspond to LC86P6032. * LC86P6032 Options
Option Configuration of input/output ports Pins, Circuits Port 0 (Can be specified for each bit.) Port 1 (Can be specified for each bit.) Port 7 pull-up MOS transistor Port 7 (Can be specified for each bit.) Option Settings 1. Input : No pull-up MOS transistor Output : N-channel open drain 2. Input : Pull-up MOS transistor Output : CMOS 1. Input : Programmable pull-up MOS transistor Output : N-channel open drain 2. Input : Programmable Pull-up MOS transistor Output : CMOS 1. Pull-up MOS transistor not provided. 2. Pull-up MOS transistor provided.
* A kind of option not corresponding LC86P6032
Option Pull-down resistor of high voltage withstand output terminal Pins, Circuits *S0/T0 to S6/T6 *S16 to S23 *S24 to S29 (specified in a bit) LC86P6032 Not provided Provided(fixed) Not provided LC866032/28/24/20/16/12/08 Specified by the option Specified by the option Specified by the option
The port operation related to the option is different at reset. Please refer to the next table.
No.4212-2/22
LC86P6032 * Port configuration at reset
Pin P0 Option settings Input : No pull-up MOS transistor Output : N-channel open drain Input : Pull-up MOS transistor Output : CMOS LC86P6032 (Same as for the mask version) Input mode *The Pull-up MOS transistor is not present during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS transistor is present. (Output is OFF) (Same as for the mask version) LC866032/28/24/20/16/12/08 Input mode without pull-up MOS transistor (Output is OFF) Input mode with pull-up MOS transistor (Output is OFF)
P1
P7
Input : Programmable pull-up MOS transistor Output : N-channel open drain Input : Programmable pull-up MOS transistor Output : CMOS Pull-up MOS transistor not provided Pull-up MOS transistor provided
Input mode without pull-up MOS transistor (Output is OFF) Input mode without pull-up MOS transistor (Output is OFF) Input mode without pull-up MOS transistor Input mode with pull-up MOS transistor
(Same as for the mask version)
(Same as for the mask version) Input mode *The Pull-up MOS transistor is not present during reset or several hundred microseconds after releasing reset. After that, the pull-up MOS transistor is present.
(2) Option The option data is created by the option specified program "SU866000.EXE". The created option data is linked to the program area by the linkage loader "L866000.EXE". (3) ROM space LC86P6032 and LC866000 series use 256 bytes that is addressed on 07F00H to 07FFFH in the program memory as the option specified data area. These program memory capacity are 32512 bytes that is addressed on 0000H to 7EFFH.
Option data 7FFFH 7F00H area 256 bytes 7EFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH 0000H 32K LC866032 LC86P6032 28K LC866028 24K LC866024 20K LC866020 16K LC866016 12K LC866012 8K LC866008 Option Data Area Option Data Area Option Data Area Option Data Area Option Data Area Option Data Area
(4) Ordering information 1.When ordering identical mask ROM and PROM devices simultaneously. Provide an EPROM containing the target memory contents together with separate order forms for each of the mask ROM and PROM versions. 2. When ordering a PROM device. Provide an EPROM containing the target memory contents together with an order form.
No.4212-3/22
LC86P6032
How to use
(1) Specification of option LC86P6032 is programmed after specifying option data. The option is specified by the SU866000.EXE. The specified option file and the file created by our macro assembler (M866000.EXE) are linked by our linker (L866000.EXE) which creates HEX file, then the option code is put in the option specified area (07F00H to 07FFFH) of its HEX file. (2) How to program for the EPROM The LC86P6032 can be programmed by an EPROM programmer with attachments W86EP6032D and W86EP6032Q. - Recommended EPROM programmer
Supplier Advantest Andou AVAL Minato electronics EPROM programmer R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL 1890A
- "27512 (Vpp=12.5V) Intel high-speed programming" mode available. The address must be set to "0000H to 07FFFH" and the jumper (DASEC) must be set `OFF' at programming. (3) How to use the data security function "Data security" is a function to prevent EPROM data from being read. Instructions on using the data security function : 1. Set the jumper of attachment "ON". 2. Attempt to program the EPROM. The EPROM programmer will display an error. The error indication is a result of normal activity of the data security feature. This is not a problem with the EPROM programmer chip.
(Notes) * The data security function is not carried out when the data of all addresses contain "FF" at step 2 above. * Data security cannot be executed when the sequential operation "BLANK=>PROGRAM=>VERIFY" is used at step 2 above. * Set the jumper "OFF" after execution of data security.
1 pin mark of LSI Data security Data security
1 pin
Not data security 1 pin W86EP6032Q W86EP6032D
Not data security
No.4212-4/22
LC86P6032
Pin Assignment
P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ P17/PWM TEST1 RES XT1 XT2 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P70/INT0 P71/INT1 72/INT2/T0IN 73/INT3/T0IN S0/T0 S1/T1 S2/T2 S3/T3 S4/T4 S5/T5 S6/T6 S7/T7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P07 P06 P05 P04 P03 P02 P01 P00 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 VP VDDVPP S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8
Package Dimension (unit : mm)
3071
SANYO : DIP-64S(750mil)
No.4212-5/22
LC86P6032
Pin Assignment
P14/SI1/SB1 P11/SI0/SB0 P15/SCK1 P12/SCK0 P17/PWM P16/BUZ P13/SO1 P10/SO0
P07
P06
P05
P04
P03
P02
P01 34
48
47
46
45
44
43
42
41
40
39
38
37
36
35
TEST1 RES XT1 XT2 VSS CF1 CF2 VDD P80/AN0 P81/AN1 P82/AN2 P83/AN3 P70/INT0 P71/INT1 72/INT2/T0IN 73/INT3/T0IN
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 10 11 12 13 14 15 64 1 2 3 4 5 6 7 8 9
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 17
P00
S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 VP VDDVPP
S0/T0
S1/T1
S2/T2
S3/T3
S4/T4
S5/T5
S6/T6
S7/T7
S8/T8
S9/T9
S10/T10
S11/T11
S12/T12
S13/T13
S14/T14
Package Dimension (unit : mm)
3159
S15/T15
SANYO : QIP-64E Notes * The QFP packages should be heat-soaked for 24 hours at 125C immediately prior to mounting (This baking is called pre-baking). * After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. Please solder within 8 hours.
No.4212-6/22
LC86P6032
System Block Diagram
Interrupt Control
IR
PLA
A15-A0 D7-D0 TA CE OE DASEC VDDVPP
Stand-by Control
PROM Control
Clock Generator
CF RC X'tal
PROM(32KB)
PC
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 7
C Register
Timer 0
Port 8 ALU
Timer 1
ADC
PSW
INT0 to 3 Noise Rejection Filter
RAR
Real Time Service
RAM
XRAM (128 bytes)
Stack Pointer
Port 0 VFD Controller Watch dog Timer High Voltage Output
No.4212-7/22
LC86P6032
Pin Description
Pin Description Table
Pin name VSS VDD VP VDDVPP PORT0 P00 to P07 I/O I/O Function Description Power supply pin (-) Power supply pin (+) Power supply pin (-) for the VFD output pull-down resist Power supply pin (+) *6 *8-bit Input / output port *Input for port 0 interrupt *Input/output in nibble units *Input for HOLD release Option Function in PROM mode
Power for programming *Pull-up resistor : Present/Not present *Output form : CMOS/N-channel open drain Output form : CMOS/N-channel open drain
PORT1 P10 to P17
I/O
PORT7 P70 P71 to P73 I/O I
PORT8 P80 to P83 S0/T0 to S6/T6 *7 S7/T7 to S15/T15 *8 S16 to S23 *9 S24 to S29 *10 RES
I
O O
*8-bit input/output port *Data direction can be specified for each bit. *Other pin functions P10 : SIO0 data output P11 : SIO0 data input/bus input/output P12 : SIO0 clock input/output P13 : SIO1 : data output P14 : SIO1 : data input/bus input/output P15 : SIO1 clock input/output P16 : Buzzer output P17 : Timer 1 output (PWM output) *4-bit input port *Pull-up resistor : *Other pin functions Present/Not present P70 : INT0 input/HOLD release/N-channel Tr. output for watchdog timer P71 : INT1 input/HOLD release P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 event input *Interrupt received format, vector address Rising Falling Rising H level L level Vector /falling Enable Enable Disable Enable Enable 03H INT0 INT1 Enable Enable Disable Enable Enable 0BH INT2 Enable Enable Enable Disable Disable 13H INT3 Enable Enable Enable Disable Disable 1BH *4-bit input port *Other pin functions AD input port (4 port pins) Output for VFD display controller segment/timing in common *Output for VFD display controller segment/timing in common *Internal pull-down resistor output *Output for VFD display controller segment *Internal pull-down resistor output *Output for VFD display controller segment Reset pin
Data input/output D0 to D7
Input of PROM control signal *DASEC (*1) * OE (*2) * CE (*3)
*S14/T14 : TA (*4) *S15/T15 : A14 (*5)
O
Address input A13 to A0
O
I
No.4212-8/22
LC86P6032
Pin name TEST1 XT1 XT2 CF1 CF2
I/O O I O I O
Function Description Test pin Should be left open Input pin for 32.768kHz crystal oscillation When not used, connect to VDD Output pin for 32.768kHz crystal oscillation When not used, should be left open Input pin for ceramic resonator oscillation Output pin for ceramic resonator oscillation
Option
Function in PROM mode
* All port options can be specified in bit units. *1 *2 *3 *4 *5 *6 Memory select input for data security Output enable input Chip enable input TA ! PROM control signal input A14 ! Address input Connect as shown in the following figure to reduce noise into VDD pin. * Short-circuit the VDD pin to the VDDVPP pin.
LSI VDD Power Supply VDDVPP VSS
*7 *8 *9 *10
S0/T0 to S6/T6 : not provided the pull-down resistor S7/T7 to S15/T15 : provided the pull-down resistor (fixed) S16 to S23 : provided the pull-down resistor (fixed) S24 to S29 : not provided the pull-down resistor
No.4212-9/22
LC86P6032 1. Absolute Maximum Ratings at VSS=0V and Ta=25C
Parameter Supply voltage Input voltage Symbol VDDMAX VI(1) VI(2) VO VIO IOPH(1) IOPH(2) IOPH(3) IOAH(1) IOAH(2) IOAH(3) IOPL(1) IOPL(2) IOAL(1) IOAL(2) Pdmax(1) Pdmax(2) Topr Tstg Pins VDD,VDDVPP *Ports 71,72,3,8 * RES VP *S0/T0 to S15/T15 *S16 to S29 *Ports 0, 1 *Port 70 Ports 0, 1 S0/T0 to S15/T15 S16 to S29 Port 0 Port 1 *S0/T0 to S15/T15 *S16 to S29 Ports 0, 1 Port 70 Port 0 Ports 1, 70 DIP64S QFP64E Conditions Ratings VDD[V] min. -0.3 -0.3 VDD-4.5 VDD-4. 5 -0.3 *CMOS output *At each pin *At each pin *At each pin Total of all pins Total of all pins Total of all pins At each pin At each pin Total of all pins Total of all pins Ta=-30 to+70C Ta=-30 to+70C -30 -65 -4 -30 -15 -10 -10 -130 20 15 40 40 760 430 +70 +150 mW C typ. max. +7.0
VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3
unit V
Output voltage Input/Output voltage High Peak level output output current current Total output current Peak output current Total output current Power dissipation (max.) Operating temperature range Storage temperature range Low level output current
mA
Notes * The QFP packages should be heat-soaked for 24 hours at 125C immediately prior to mounting (This baking is called pre-baking). * After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. Please solder within 8 hours.
No.4212-10/22
LC86P6032 2. Recommended Operating Range at Ta=-30C to +70C, VSS=0V
Parameter Operating supply voltage range Hold voltage Symbol VDD VDD Pins Conditions 0.98s tCYC 400s RAM and registers retain their pre-HOLD mode values 4.5 to 6.0 Output disable Output disable Ratings VDD[V] min. 4.5 typ. max. 6.0 unit V
VHD
VDD
2.0
6.0
Pull-down voltage Input high voltage
VP VIH(1) VIH(2)
VP Port 0 (Schmitt) *Port 1 *Ports 72,73 (Schmitt) *Port 70 port input/interrupt *Port 71 (Schmitt) * RES Port 70 Watchdog timer Port 8 Port 0 (Schmitt) *Port 1 *Ports 72,73 (Schmitt) *Port 70 port input/interrupt *Port 71 (Schmitt) * RES Port 70 Watchdog timer Port 8
-35
VDD VDD VDD
4.5 to 6.0 0.4VDD +0.9 4.5 to 6.0 0.75VDD
VIH(3)
Output N-channel Tr. OFF
4.5 to 6.0 0.75VDD
VDD
VIH(4) VIH(5) VIL(1) VIL(2)
Output N-channel Tr. OFF Output disable Output disable
4.5 to 6.0 0.9VDD 4.5 to 6.0 0.75VDD 4.5 to 6.0 VSS 4.5 to 6.0 VSS
VDD VDD 0.2VDD 0.25VDD
Input low voltage
VIL(3)
N-channel Tr. OFF
4.5 to 6.0
VSS
0.25VDD
VIL(4) VIL(5) tCYC
N-channel Tr. OFF
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
VSS VSS 0.98
Operation cycle time
0.8VDD -1.0 0.25VDD 400
s
continue
No.4212-11/22
LC86P6032
Parameter Oscillation frequency range (Note 1)
Symbol FmCF(1)
Pins CF1,CF2
Conditions *12MHz (ceramic resonator oscillation) *Refer to figure 1 *3MHz (ceramic resonator oscillation) *Refer to figure 1 RC oscillation *32.768kHz (crystal resonator oscillation) *Refer to figure 2 *12MHz (ceramic resonator oscillation) *Refer to figure 3 *3MHz (ceramic resonator oscillation) *Refer to figure 3 *32.768kHz (crystal resonator oscillation) *Refer to figure 3
Ratings VDD[V] 4.5 to 6.0 min. 11.76 typ. 12 max. 12.24
unit MHz
FmCF(2)
CF1,CF2
4.5 to 6.0
2.94
3
3.06
FmRC FsXtal XT1,XT2
4.5 to 6.0 4.5 to 6.0
0.4
0.8 32.768
2.0 kHz
Oscillation stable time period (Note 1)
tmsCF(1) CF1,CF2
4.5 to 6.0
0.02
0.2
ms
tmsCF(2) CF1,CF2
4.5 to 6.0
0.1
1
tssXtal
XT1,XT2
4.5 to 6.0
1
1.5
s
(Note 1)
The oscillation constants are shown on Table 1 and Table 2.
No.4212-12/22
LC86P6032 3. Electrical Characteristics at Ta=-30C to +70C, VSS=0V
Parameter Input high current Symbol IIH(1) Pins *Port 1 *Port 0 without pull-up MOS Tr. Conditions *Output disabled *Pull-up MOS Tr. OFF *VIN=VDD (including off-state leak current of output Tr.) VIN=VDD Ratings VDD[V] 4.5 to 6.0 min. typ. max. 1 unit A
IIH(2)
Input low current
IIH(3) IIL(1)
*Port 7 without pull-up MOS Tr. *Port 8 RES *Port 1 *Port 0 without pull-up MOS Tr.
4.5 to 6.0
1
IIL(2)
Output high voltage
IIL(3) VOH(1) VOH(2) VOH(3) VOH(4)
*Port 7 without pull-up MOS Tr. *Port 8 RES Ports 0, 1 at CMOS output S0/T0 to S15/T15
VIN=VDD *Output disabled *Pull-up MOS Tr. OFF *VIN=VSS (including off-state leak current of output Tr.) VIN=VSS
4.5 to 6.0 4.5 to 6.0
1 -1
4.5 to 6.0
-1
VOH(5) VOH(6)
S16 to S29
Output low voltage
VOL(1) VOL(2)
Ports 0, 1
Pull-up MOS Tr. resistance
VOL(3) Rpu
Port 70 *Ports 0, 1 *Port 7
VIN=VSS IOH=-1.0mA IOH=-0.1mA IOH=-20mA *IOH=-1mA *The current IOH at each pin should be between 0 and -1mA. IOH=-5mA *IOH=-1mA *The current IOH at each pin should be between 0 and -1mA. IOL=10mA *IOL=1.6mA *When the total current of the ports 0, 1 is not over 40mA. IOL=1mA VOH=0.9VDD
4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0
-1 VDD-1
VDD-0.5 VDD-1.8
V
VDD-1
4.5 to 6.0 VDD-1.8 4.5 to 6.0 VDD-1
4.5 to 6.0 4.5 to 6.0
1.5 0.4
4.5 to 6.0 4.5 to 6.0
15
40
0.4 70
K
continue
No.4212-13/22
LC86P6032
Parameter Output offleakage current Pull-down resistor Hysteresis voltage Pin capacitance
Symbol IOFF(1) IOFF(2) Rpd
Pins
Conditions
Ratings VDD[V] 4.5 to 6.0 4.5 to 6.0 5.0 min. -1 -30 60 100 200 typ. max.
unit A
S0/T0 to S6/T6, *Output P-ch Tr. OFF S24 to S29 without *VOUT=VSS pull-down resistor *Output P-ch Tr. OFF
*VOUT=VDD-40V
VHIS
CP
S7/T7 to S15/T15, S16 to S23 with pull-down resistor *Ports 0, 1 *Port 7 * RES All pins
*Output P-ch Tr. OFF *VOUT=3V *Vp=-30V
K
Output disable
4.5 to 6.0
0.1VDD
V
*f=1MHz *Unmeasured input
4.5 to 6.0
10
pF
pins are set to VSS level
*Ta=25C
4. Serial Input/Output Characteristics at Ta=-30C to +70C, VSS=0V
Parameter Cycle Low-level pulse width High-level pulse width Cycle Low-level pulse width High-level pulse width Data set up time Input clock Symbol tCKCY(1) tCKL(1) tCKH(1) tCKCY(2) tCKL(2) tCKH(2) tICK *SI0,SI1 *SB0,SB1 SCK0, SCK1 *Use pull-up resistor (1k) when set to opendrain output. *Refer to figure 5. *Data set-up to SCK0,1 *Data hold from SCK0,1 *Refer to figure 5. *Use pull-up resistor (1k) when set to opendrain output. *Data hold from SCK0,1 *Refer to figure 5. Pins SCK0, SCK1 Conditions Refer to figure 5. Ratings VDD[V] 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 0.1 min. 2 1 1 2 1/2 tCKCY 1/2 tCKCY s typ. max. unit tCYC
Serial clock Serial input
Output clock
Data hold time Output delay time (Serial clock is external clock) Output delay time (Serial clock is internal clock)
tCKI tCKO(1) *SO0,SO1 *SB0,SB1
4.5 to 6.0 4.5 to 6.0
0.1 7/12 tCYC
+0.2
Serial output
tCKO(2)
4.5 to 6.0
1/3 tCYC
+0.2
No.4212-14/22
LC86P6032 5. Pulse Input Conditions at Ta=-30C to +70C, VSS=0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) Pins *INT0, INT1 *INT2/T0IN INT3/T0IN (The noise rejection clock selected to 1/1.) INT3/T0IN (The noise rejection clock selected to 1/64.)
RES
Conditions *Interrupt acceptable *Timer0 pulse countable *Interrupt acceptable *Timer0 pulse countable *Interrupt acceptable *Timer0 pulse countable Reset acceptable
Ratings VDD[V] 4.5 to 6.0 min. 1 typ. max.
unit tCYC
4.5 to 6.0
2
tPIH(3) tPIL(3)
4.5 to 6.0
128
tPIL(4)
4.5 to 6.0
200
s
6. AD Converter Characteristics at Ta=-30C to +70C, VSS=0V
Parameter Resolution Absolute precision Conversion time Symbol N ET tCAD Pins Conditions Ratings VDD[V] 4.5 to 6.0 4.5 to 6.0 4.5 to 6.0 min. typ. 8 15.68 (tCYC= 0.98s) 31.36 (tCYC= 0.98s) 4.5 to 6.0 VAIN=VDD VAIN=VSS 4.5 to 6.0 4.5 to 6.0 VSS max. unit bit 1.5 LSB 65.28 s (tCYC= 4.08s) 130.56 (tCYC= 4.08s) VDD 1 -1 V A
(Note 2) AD conversion time = 16 x tCYC (ADCR2=0) (Note 3) AD conversion time = 32 x tCYC (ADCR2=1) (Note 3) AN0 to AN3
Analog input voltage range Analog port input current
VAIN IAINH IAINL
(Note 2) Quantizing error (1/2 LSB) is ignored. (Note 3) The conversion time is the period from execution of the instruction to start conversion to the completion of shifting the A/D converted value to the register.
No.4212-15/22
LC86P6032 7. Current Drain Characteristics at Ta=-30C to +70C, VSS=0V
Parameter Current drain during basic operation (Note 4) Symbol IDDOP(1) Pins VDD Conditions *FmCF=12MHz for Ceramic resonator oscillation *FsXtal=32.768kHz for crystal oscillator *System clock : CF oscillator *Internal RC oscillator stopped *FmCF=3MHz for Ceramic resonator oscillation *FsXtal=32.768kHz for crystal oscillator *System clock : CF oscillator *Internal RC oscillator stopped *FmCF=0Hz (when oscillator stops) *FsXtal=32.768kHz for crystal oscillator *System clock : RC oscillator *FmCF=0Hz (when oscillator stops) *FsXtal=32.768kHz for crystal oscillator *System clock : crystal oscillator *Internal RC oscillator stopped Ratings VDD[V] 4.5 to 6.0 min. typ. 13 max. 26 unit mA
IDDOP(2)
4.5 to 6.0
6.5
14
IDDOP(3)
4.5 to 6.0
4
10
IDDOP(4)
4.5 to 6.0
3.5
9
Continue.
No.4212-16/22
LC86P6032
Ratings VDD[V] 4.5 to 6.0 min. typ. 5 max. 10
Parameter
Symbol
Pins
Conditions *HALT mode *FmCF=12MHz for Ceramic resonator oscillation *FsXtal=32.768kHz for crystal oscillator *System clock : CF oscillator *Internal RC oscillator stopped *HALT mode *FmCF=3MHz for Ceramic resonator oscillation *FsXtal=32.768kHz for crystal oscillator *System clock : CF oscillator *Internal RC oscillator stopped *HALT mode *FmCF=0Hz (when oscillator stops) *FsXtal=32.768kHz crystal oscillator *System clock : RC oscillator *HALT mode *FmCF=0Hz (when oscillator stops) *FsXtal=32.768kHz for crystal oscillator *System clock : crystal oscillator *Internal RC oscillator stopped HOLD mode
unit mA
Current drain at IDDHALT(1) VDD HALT mode (Note 4)
IDDHALT(2)
4.5 to 6.0
1.8
4.6
IDDHALT(3)
4.5 to 6.0
400
800
A
IDDHALT(4)
4.5 to 6.0
20
60
Current drain at IDDHOLD(1) VDD HOLD mode IDDHOLD(2) (Note 4)
4.5 to 6.0 2.5 to 4.5
0.05 0.02
30 20
(Note 4) The currents of output transistors and pull-up MOS transistors are ignored.
No.4212-17/22
LC86P6032 Table 1. Ceramic resonator oscillation circuit recommended constants (main-clock)
Oscillation type 12MHz ceramic resonator oscillation Supplier Murata Oscillator CSA12.0MTZ CSA12.0MT CST12.0MTW KBR-12.0M CSA3.00MG CST3.00MGW KBR-3.0MS C1 33pF 33pF on chip 33pF 33pF on chip 47pF 47pF 33pF 33pF C2 33pF 33pF
3MHz ceramic resonator oscillation
Kyocera Murata Kyocera
* For both C1 and C2, the K rank (10%) and SL characteristics must be used. Table 2. Crystal oscillation circuit recommended constants (sub-clock)
Oscillation type 32.768kHz crystal oscillation Supplier Daishinku Kyocera Oscillator DT-38(1TA252E00) KF-38G-13P0200 C3 18pF 18pF C4 18pF 18pF
(Notes)
*Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. *If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
CF C1 C2 C3
X'tal C4
Figure 1
Ceramic resonator oscillation
Figure 2
Crystal oscillation
No.4212-18/22
LC86P6032
VDD Power supply VDD limit 0V Reset time
RES
Internal RC resontor oscillation tmsCF CF1, CF2 tssXtal XT1, XT2
Operation mode Unfixed
Reset
Instruction execution mode
< Reset time and oscillation stable time. >
HOLD release signal
Valid
Internal RC resontor oscillation tmsCF CF1, CF2 tssXtal XT1, XT2
Operation mode HOLD
Instruction execution mode
< Hold release signal and oscillation stable time. > Figure 3 Oscillation stable time
VDD
RRES RES CRES
(Note) The values of CRES and RRES should be determined such that reset time is at least 200s, measured from the moment the power exceeds the VDD lower limit. Figure 4 Reset circuit
No.4212-19/22
LC86P6032
0.5VDD

tCKCY tCKL SCK0 SCK1 tICK SI0 SI1 tCKO SO0, SO1 SB0, SB1 50pF tCKI tCKH
VDD
1K

Figure 5
Serial input/output test conditions
tPIL
tPIH
Figure 6
Pulse input timing conditions
No.4212-20/22
LC86P6032
Notice for use
* The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for SANYO to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown in the following figure should always be followed. * It is not possible to perform a writing test on the blank PROM.. 100% yield, therefore, cannot be guaranteed. * Should be stored in dry conditions (QFP type only) The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. * After opening the packing (QFP type only) The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the substrate. After opening the packing, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. Please solder within 8 hours.
a. Shipping with a blank PROM (Data to be programmed by customer) This microcomputer is provided DIP/QFP packages, but the condition before mounting is not same. Refer to the mounting precedure as follows;
DIP
QFP
Programming and verifying
Programming and verifying
Recommended process of screening Heat-soak 1505C, 24 +1 Hr -0
Recommended process of screening Heat-soak 1505C, 24 +1 Hr -0
Program reading test
Program reading test
Baking before mounting 125C, 24 hours Baking
Mounting
Mounting
No.4212-21/22
LC86P6032 b. Shipping with programmed PROM (Data programmed by Sanyo)
DIP
QFP
Baking before mounting 125C, 24 hours Baking
Mounting
Mounting
PS No.4212-22/22

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